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QUAD NON-PROGRAMMABLE PCM CODEC
FEATURES
* * *
IDT821024
DESCRIPTION
The IDT821024 is a single-chip, four channel PCM CODEC with onchip filters. The device provides analog-to-digital and digital-to-analog conversions and supports both a-law and -law companding. The digital filters in IDT821024 provides the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. All of the digital filters are performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fixed filters set the transmit and receive gain and frequency response. In the IDT821024 the PCM data is transmitted to and received from the PCM highway in time slots determined by the individual Frame Sync signals (FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both Long and Short Frame Sync modes are available in the IDT821024. The IDT821024 can be used in digital telecommunication applications such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/ Data Access Unit.
* * * * * * *
4 channel CODEC with on-chip digital filters Selectable A-law or -law companding Master clock frequency selection: 2.048 MHz, 4.096 MHz or 8.192 MHz - Internal timing automatically adjusted based on MCLK and frame sync signal Separate PCM and master clocks Single PCM port with up to 8.192 MHz data rate (128 time slots) Transhybrid balance impedance hardware adjustable via external components Transmit gains hardware adjustable via external components Low power +5.0 V CMOS technology +5.0 V single power supply Package available: 32 pin PLCC, 44 pin TQFP
FUNCTIONAL BLOCK DIAGRAM
IIN1 VOUT1 IIN2 VOUT2 IIN3 VOUT3
Anolog Front End CH1
PCM TSA 1 PCM TSA 2 PCM TSA 3 PCM TSA 4
FSX1 FSR1 FSX2 FSR2 FSX3 FSR3 FSX4 FSR4 DX TSC DR PCLK
Anolog Front End CH2
DSP
Anolog Front End CH3
IIN4 VOUT4
Anolog Front End CH4
PCM Interface
MCLK IREF CNF
Clock & Reference Circuits
PDN 1~ 4
Control
A/
AGND
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
1
(c)2003 Integrated Device Technology, Inc.
DGND
VCCA
VCCD
APRIL 3, 2003
DSC-6034/4
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
VOUT1 MCLK 30 PDN1 PDN2 PDN3 32 PDN4 31 CNF 3
4
2
1
IIN1 IIN2 VOUT2 VCCA IREF AGND VOUT3 IIN3 IIN4
5 6 7 8 9 10 11 12 14 15 16 17 18 19 13
29 28 27
PCLK TSC DGND DX VCCD DR FSR1 FSX1 FSR2
32-Pin PLCC
26 25 24 23 22 21 20 FSX2 MCLK 35
VOUT4
FSX4
FSR4
FSX3
VOUT1
FSR3
A/
44
43
42
41
40
39
38
37
36
34
PCLK
PDN1
PDN2
PDN3
PDN4
CNF
IIN1
NC
NC
IIN2 VOUT2 NC NC VCCA IREF AGND NC NC VOUT3 IIN3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 32 31
NC NC TSC DGND NC DX VCCD DR FSR1 FSX1 FSR2
44-Pin TQFP
30 29 28 27 26 25 24 23
VOUT4
FSX4
FSX3
FSR4
2
FSR3
FSX2
NC
NC
IIN4
A/
NC
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Name AGND VCCA DGND VCCD DR I/O ----I Pin Number PLCC TQFP 10 8 27 25 24 7 5 30 27 26 Description Analog Ground. All ground pins should be connected to the ground plane of the circuit board. +5 V Analog Power Supply. All power supply pins should be connected to the power plane of the circuit board. Digital Ground. All ground pins should be connected to the ground plane of the circuit board. +5 V Digital Power Supply. All power supply pins should be connected to the power plane of the circuit board. Receive PCM Data Input. The PCM data for Channel 1, 2, 3 and 4 is shifted serially into DR pin by the Receive Frame Sync Signal (FSR) with MSB first. A byte of data for each channel is received every 125 s at the PCLK rate. Transmit PCM Data Output. The PCM data for Channel 1, 2, 3 and 4 is shifted serially out to the DX pin by the Transmit Frame Sync Signal (FSX) with MSB first. A byte of data for each channel is transmitted every 125 s at the PCLK rate. DX is high impedance between time slots. Receive Frame Sync Input for Channel 1/2/3/4 This 8kHz signal pulse identifies the receive time slot for Channel N on a system's receive PCM frame. It must be synchronized to PCLK. Transmit Frame Sync Input for Channel 1/2/3/4 This 8 kHz signal pulse identifies the transmit time slot for Channel N on a system's transmit PCM frame. It must be synchronized to PCLK. Reference Current. The IREF output is biased at the internal reference voltage. A resistor placed from IREF to ground sets the reference current used by the analog-to-digital converter to encode the signal current present on IINn pin (n is channel number, n = 1 to 4) into digital form. Voice Frequency Receiver Output for Channel 1/2/3/4 This is the output of receiver amplifier for Channel N. The received digital data from DR is processed and converted to an analog signal at this pin. Voice Frequency Transmitter Input for Channel 1/2/3/4 This is the input to the gain setting amplifier in the transmit path for Channel N. The analog voice band voltage signal is applied to this pin through a resistor. This input is a virtual AC ground input, which is biased at the IREF pin. Master Clock. The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The IDT821024 determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the FSX frequency. PCM Clock. The PCM Clock shifts out the PCM data to the DX pin and shifts in PCM data from the DR pin. The PCM clock frequency is an integer multiple of the frame sync frequency. When PCLK is connected to MCLK, the PCM clock can generate the DSP clock as well. Time Slot Control. This open drain output is low active. When the PCM data is transmitted to the DX pin for any of the four channels, this pin will be pulled low. A/ -Law Selection. When this pin is low, -Law is selected; when this pin is high, A-Law is selected. This pin can be connected to VCCD or DGND pin directly.
DX
O
26
28
FSR1 FSR2 FSR3 FSR4 FSX1 FSX2 FSX3 FSX4
I
23 21 19 17 22 20 18 16
25 23 21 19 24 22 20 18
I
IREF
O
9
6
VOUT1 VOUT2 VOUT3 VOUT4 IIN1 IIN2 IIN3 IIN4
O
4 7 11 14 5 6 12 13
43 2 10 13 44 1 11 12
I
MCLK
I
30
35
PCLK
I
29
34
TSC
O
28
31
A/
I
15
16
3
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (cont'd)
Name PDN1 PDN2 PDN3 PDN4 CNF I/O Pin Number PLCC TQFP 2 1 32 31 3 39 38 37 36 41 3, 4, 8, 9, 14, 15, 17, 29, 32, 33, 40, 42 Description Channel 1/2/3/4 Power Down. When this pin is high, Channel N is powered down. Capacitor For Noise Filter. This pin should be connected to AGND through a 0.1 F capacitor.
I
O
NC
--
No connection
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
and compressed to PCM format. Transmit PCM Interface The transmit PCM interface clocks out 1 byte (8 bits) PCM data out of DX pin every 125 s. The transmit logic, synchronized by the Transmit Frame Sync signal (FSXn), controls the data transmission. The FSXn pulse identifies the transmit time slot of the PCM frame for Channel N. The PCM Data is transmitted serially on DX pin with the Most Significant Bit (MSB) first. When the PCM data is being output on DX pin, the TSC signal will be pulled low. Receive Signal Processing In the receive path, the PCM code is received at the rate of 8,000 samples per second. The PCM code is expanded and sent to the DSP for interpolation. A receive filter is implemented in the DSP as a digital lowpass filter. The filtered signal is then sent to an oversampling DAC. The DAC output is post-filtered and delivered at VOUT pin by an amplifier. The amplifier can drive resistive load higher than 2 K. Receive PCM Interface The receive PCM interface clocks 1 byte (8 bits) PCM data into DR pin every 125 s. The receive logic, synchronized by the Receive Frame Sync signal (FSRn), controls the data receiving process. The FSRn pulse identifies the receive time slot of the PCM frame for Channel N. The PCM Data is received serially on DR pin with the Most Significant Bit (MSB) first. Hardware Gain Setting In Transmit Path The transmit gain of the IDT821024 for each channel can be set by 2 resistors, RREF and RTXn (as shown in Figure 1), according to the following equation:
Gt = 3 x R REF R TXn
The IDT821024 contains four channel PCM CODEC with on chip digital filters. It provides the four-wire solution for the subscriber line circuitry in digital switches. The device converts analog voice signal to digital PCM data, and converts digital PCM data back to analog signal. Digital filters are used to bandlimit the voice signals during the conversion. Either A-law or -law is supported by the IDT821024. The law selection is performed by A/ pin. The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096 MHz, or 8.192 MHz. Internal circuitry determines the master clock frequency automatically. The serial PCM data for four channels are time multiplexed via two pins, DX and DR. The time slots of the four channels are determined by the individual Frame Sync signals at rates from 256 kHz to 8.192 MHz. For each channel, the IDT821024 provides a transmit Frame Sync signal and a receive Frame Sync signal. Each channel of the IDT821024 can be powered down independently to save power consumption. The Channel Power Down Pins PDN1-4 configure channels to be active (power-on) or standby (power-down) separately. Signal Processing High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) are used in the IDT821024 to provide the required conversion accuracy. The associated decimation and interpolation filtering are realized with both dedicated hardware and Digital Signal Processor (DSP). The DSP also handles all other necessary functions such as PCM bandpass filtering and sample rate conversion. Transmit Signal Processing In the transmit path, the analog input signal is received by the ADC and converted into digital data. The digital output of the oversampling ADC is decimated and sent to the DSP. The transmit filter is implemented in the DSP as a digital bandpass filter. The filtered signal is further decimated
The receive gain of IDT821024 is fixed and equal to 1.
to SLIC VTX
IDT821024 RTX1 CTX1 VIN1
A/D IREF
Bal Net
VREF to IREF
IREF1 VREF1
RREF1 CFIL
to SLIC RSN
RRX1
CRX1
VOUT1
VREF D/A
Figure 1. IDT821024 Transmit Gain Setting for Channel 1
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
OPERATING THE IDT821024
The following descriptions about operation applies to all four channels of the IDT821024. Power-on Sequence and Master Clock Configuration To power on the IDT821024 users should follow this sequence: 1. Apply ground; 2. Apply VCC, finish signal connections; 3. Set PDN1-4 pins high, thus all of the 4 channels are powered down; The master clock (MCLK) frequency of IDT821024 can be configured as 2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync (FSX) inputs, the device determines the MCLK frequency and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the Frame Sync frequency. Operating Modes There are two operating modes for each transmit or receive channel: standby mode (when the channel is powered down) and normal mode (when the channel is powered on). The mode selection of each channel is done by its corresponding PDN pin. When PDNn is 1, Channel N is in standby mode; when PDNn is 0, Channel N is in normal mode. In standby mode, all circuits are powered down with the analog outputs placed in high impedance state. In normal mode, each channel of the IDT821024 is able to transmit and receive both PCM and analog information. The normal mode is used when a telephone call is in progress. Companding Law Selection An A/ pin is provided by IDT821024 for the companding law selection. When this pin is low, -law is selected; when the pin is high, A-law is selected.
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Rating Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature Com'I & Ind'I 6.5 -0.5 to 5.5 600 -65 to +150 Unit V V mW C
RECOMMENDED DC OPERATING CONDITIONS
Parameter Operating Temperature Power Supply Voltage Min. -40 4.75 Typ. Max. +85 5.25 Unit C V
NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of 50 ppm
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS
Digital Interface
Parameter VIL VIH VOL Description Input Low Voltage Input High Voltage Output Low Voltage Min 2.0 0.4 0.8 0.2 VOH Output High Voltage VDD-0.6 VDD-0.2 II IOZ CI Input Current Output Current in High-impedance State Input Capacitance -10 -10 10 10 5 Typ Max 0.8 Units V V V V V V V A A pF Test Conditions All digital inputs All digital inputs DX, TSC,IL = 14mA All other digital outputs, IL = 4mA. All digital pins, IL = 14mA DX, IH = -7 mA, all other outputs, IH = -4 mA All digital pins, IH = -1mA Any digital inputs GNDNote: Total current must not exceed absolute maximum ratings.
Power Dissipation
Parameter PD2 PD1 PD0 Description Operating Power Dissipation 1 Operating Power Dissipation 1 Standby Power Dissipation Min Typ 180 60 4 Max 240 90 10 Units mW mW mW Test Conditions All channels are active Only one channel is active All channels are powered down,with only MCLK present
Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded
Analog Interface
Parameter VOUT1 VOUT2 RO RL I IR IIOS IOUT IZ CL Description Output Voltage Output Voltage Swing Output Resistance Load Resistance Analog Input Current Range Offset Current Allowed on IIN VOUT Output Current (F< 3400Hz) Output Leakage Current Load Capacitance Min 2.25 3.25 2000 40 -1.6 -5 -10 +1.6 5 10 100 Typ 2.4 1 Max 2.6 4 Units V V P-P A A mA A pF Test Conditions Alternating zero -law PCM code applied to DR. RL=2000 0dBm0, 1020Hz PCM code applied to DR External loading RREF = 13k
Power down External loading
7
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
TRANSMISSION CHARACTERISTICS
0dBm0 is defined as 0.6832Vrms for A-law and 0.6778 Vrms for -law, both for 600 load. Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical value are tested at VDD = 5V and TA = 25C. Absolute Gain
Parameter GXA GRA Description Transmit Gain, Absolute 0C to 85C -40C Receive Gain, Absolute 0C to 85C -40C Min -0.25 -0.35 -0.25 -0.35 Typ Max 0.25 0.35 0.25 0.35 Units dB dB dB dB Test Conditions Signal input of 0 dBm0, -law or A-law Measured relative to 0 dBm0, -law or A-law, PCM input of 0 dBm0 1020 Hz , R L = 10 k
Gain Tracking
Parameter GTX Description Transmit Gain Tracking +3 dBm0 to -40 dBm0 -40 dBm0 to -50 dBm0 -50 dBm0 to -55 dBm0 Receive Gain Tracking +3 dBm0 to -40 dBm0 -40 dBm0 to -50 dBm0 -50 dBm0 to -55 dBm0 Min -0.10 -0.25 -0.50 -0.10 -0.25 -0.50 Typ Max 0.10 0.50 0.50 0.10 0.50 0.50 Units dB dB dB dB dB dB Test Conditions Tested by Sinusoidal Method, -law/A-law
GT R
Tested by Sinusoidal Method, -law/A-law
Frequency Response
Parameter GXR Description Transmit Gain, Relative to GXA f = 50 Hz f = 60 Hz f = 300 Hz to 3400 Hz f = 3600 Hz f = 4600 Hz and above Receive Gain, Relative to GRA f below 300 Hz f = 300 Hz to 3400 Hz f = 3600 Hz f = 4600 Hz and above Min Typ Max -40 -40 0.15 -0.1 -35 0 0.15 -0.2 -35 Units dB dB dB dB dB dB dB dB dB Test Conditions
-0.15
GRR
-0.15
Group Delay
Parameter D XA D XR Description Transmit Delay, Absolute * Transmit Delay, Relative to 1800 Hz f = 500 Hz - 600 Hz f = 600 Hz -1000 Hz f = 1000 Hz - 2600 Hz f = 2600 Hz - 2800 Hz Receive Delay, Absolute * Receive Delay, Relative to 1800 Hz f = 500 Hz - 600 Hz f = 600 Hz -1000 Hz f = 1000 Hz - 2600 Hz f = 2600 Hz - 2800 Hz Min Typ Max 340 280 150 80 280 260 50 80 120 150 Units s s s s s s s s s s Test Conditions
D RA D RR
Note*: Minimum value in transmit and receive path.
8
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
Distortion
Parameter STDX Description Transmit Signal to Total Distortion Ratio A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 -law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 Receive Signal to Total Distortion Ratio A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 -law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion Min 36 36 30 24 36 36 31 27 36 36 30 24 36 36 31 27 -42 -42 -42 Typ Max Units dB dB dB dB dB dB dB dB ITU-T O.132 dB dB dB dB dB dB dB dB dBm0 dBm0 dBm0 Sine Wave Method,Psophometric Weighted for Alaw;Sine Wave Method,C Message Weighted for law; Test Conditions ITU-T O.132 Sine Wave Method,Psophometric Weighted for Alaw, C Message Weighted for -law.
STDR
SFDX SFDR IMD
200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency 3400 Hz Transmit or receive,two frequencies in the range (300 Hz- 3400 Hz) at -6 dBm0
Noise
Parameter NXC NXP NRC NRP NRS PSRX PSRR SOS Description Transmit Noise, C Message Weighted for -law Transmit Noise, Psophometric Weighted for A-law Receive Noise, C Message Weighted for -law Receive Noise, Psophometric Weighted for A-law Noise, Single Frequency f = 0 kHz - 100 kHz Power Supply Rejection Transmit f = 300 Hz - 3.4 kHz f = 3.4 kHz - 20 kHz Power Supply Rejection Receive f = 300 Hz - 3.4 kHz f = 3.4 kHz - 20 kHz Spurious Out-of-Band Signals at VOUT Relative to Input PCM code applied: 4600 Hz - 20 kHz 20 kHz - 50 kHz Min Typ Max 16 -68 12 -78 -53 Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0 dB dB dB dB -40 -30 dB dB PCM code is positive one LSB, VDD = 5.0 VDC + 100 mVrms 0 dBm0, 300 Hz - 3400 Hz input Test Conditions
IIN = 0 A, tested at VOUT VDD = 5.0 VDC + 100 mVrms
40 25 40 25
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
Interchannel Crosstalk
Parameter XT X-R XTR-X XTX-X XT R-R Description Transmit to Receive Crosstalk Receive to Transmit Crosstalk Transmit to Transmit Crosstalk Receive to Receive Crosstalk Min Typ -85 -85 -85 -85 Max -78 -80 -78 -80 Units dB dB dB dB Test Conditions 300 Hz - 3400 Hz, 0 dBm0 signal into IIN of interfering channel. Idle PCM code into channel under test. 300 Hz - 3400 Hz, 0 dBm0 PCM code into interfering channel. IIN = 0 A for channel under test. 300 Hz - 3400 Hz, 0 dBm0 signal into IIN of interfering channel. IIN = 0 A for channel under test. 300 Hz - 3400 Hz, 0 dBm0 PCM code into interfering channel. Idle PCM code into channel under test.
Intrachannel Crosstalk
Parameter XTX-R XTR-X Description Transmit to Receive Crosstalk Receive to Transmit Crosstalk Min Typ -80 -80 Max -70 -70 Units dB dB Test Conditions 300 Hz - 3400 Hz, 0 dBm0 signal into IIN. Idle PCM code into DR. 300 Hz - 3400 Hz, 0 dBm0 PCM code into DR. IIN = 0 A.
10
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
TIMING CHARACTERISTICS
Clock
Parameter t1 t2 t3 t4 t5 Description PCLK Duty Cycle PCLK Rise and Fall Time MCLK Duty Cycle MCLK Rise and Fall Time PCLK Clock Period 244 Min 40 40 Typ Max 60 25 60 15 Units % ns % ns ns Test Conditions PCLK=512kHz to 8.192MHz PCLK=512kHz to 8.192MHz MCLK=2.048Hz,4.096MHz or 8.192MHz MCLK=2.048Hz,4.096MHz or 8.192MHz PCLK=512kHz to 8.192MHz
Transmit
Parameter t11 t12 t13 t14 t15 t16 t17 t18 t19 t21 t22 Description Data Output Delay Time (for Short Frame Sync Mode) Data Hold Time Data Delay to High-Z Frame sync Hold Time Frame sync High Setup Time TSC Enable Delay Time(for Short Frame Sync Mode) TSC Disable Delay Time Data Output Delay Time(for Long Frame Sync Mode) TSC Enable Delay Time(for Long Frame Sync Mode) Receive Data Setup Time Receive Data Hold Time Min 5 5 50 50 55 5 50 5 5 25 5 Typ Max 70 70 220 t5+70 t5-50 80 220 t5+70 40 40 Units ns ns ns ns ns ns ns ns ns ns ns Test Conditions
Note: Timing parameter t13 is referenced to a high-impedance state.
MCLK
t4 t4
Figure 2. MCLK Timing
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IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
INDUSTRIAL TEMPERATURE RANGE
Time Slot PCLK t15 FSX/ FSR t11 DX BIT 1 BIT 2 t21 DR BIT 1 t16 TSC BIT 2 BIT 3 t22 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 t17 t12 BIT 4 BIT 5 BIT 6 BIT 7 t13 BIT 8 t14 1 2 t2 3 4 t2 5 t5 6 7 8
Figure 3. PCM Interface Timing for Short Frame Mode
Time Slot
PCLK
1 t15 t5
2 t2
3
4 t2
5
6
7
8
1
FSX/ FSR t18 DX BIT 1 BIT 2 t21 DR BIT 1 t19 TSC BIT 2 BIT 3 t22 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 t17 t12 BIT 4 BIT 5 BIT 6 BIT 7 t13 BIT 8
Figure 4. PCM Interface Timing for Long Frame Mode
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ORDERING INFORMATION
IDT XXXXXX Device Type XX Package X Process/ Temperature Range
Blank
Industrial (-40 C to +85 C)
J PP
Plastic Leaded Chip Carrier (PLCC, PL32) Thin Quad Flat Pack (TQFP, PP44)
821024
Quad Non-Programmable PCM CODEC
Data Sheet Document History
01/16/2002 02/21/2002 09/10/2002 01/08/2003 04/03/2003 pgs. 4, 5 pgs. 1-4, 13 pg. 8 pgs. 1, 13 pg. 1
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com*
for Tech Support: 408-330-1552 email: telecomhelp@idt.com
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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